According to gigabit Ethernet standards, a serial bit stream of data to be transmitted is spread among electrical lanes and then among optical lanes before being transmitted over a network. For example, in 100 gigabit per second (Gb) Ethernet, serial data to be transmitted is spread over ten electrical lanes that each operate at 10 Gb. The data from the ten electrical lanes is multiplexed onto four optical lanes that each operate at 25 Gb. On the receive side, the data is received on the four optical lanes, demultiplexed into ten electrical lanes, and then serialized to form the transmitted serial bit stream.
To facilitate such multiplexing and demultiplexing of the data, the data transmitted over the electrical lanes is divided into virtual lanes, and, in some cases, the total number of virtual lanes is set to the least common multiple of the number of electrical and the number of optical lanes. Continuing with the 100 Gb Ethernet example, there are ten electrical lanes and four optical lanes. The least common multiple of four and ten is twenty. Accordingly, in 100 Gb Ethernet, that data transmitted on each of the ten electrical lanes is divided into two virtual lanes for a total of twenty virtual lanes.
Each of the virtual lanes is identified by a unique virtual lane marker. The transmitter periodically inserts virtual lane markers in data to be transmitted. The virtual lane markers are transmitted with the data over the electrical lanes. The data and virtual lane markers from the electrical lanes are multiplexed and transmitted over the optical lanes. Because the mapping between electrical and optical lanes is not fixed by gigabit Ethernet standards, bits from a given virtual lane can appear on any (but only one) optical lane. The virtual lane markers allow the physical component sublayer (PCS) at the receiver to identify which virtual lane bits are multiplexed onto each optical lane. The receiver places virtual lane bits for each virtual lane in individual first-in-first-out registers (FIFOs) and does not remove data from the FIFOs until the virtual lane markers for all of the virtual lanes have been received. Once the receiver determines that all of the virtual lane markers have been received, the receiver knows that the data following the virtual lane markers across the set of FIFOs represents the original transmitted bit stream and can extract or output the bits from the FIFOs. By waiting until all of the virtual lane markers have been received before extracting the data, the receiver removes the effect of skew on the received data.
The data rate or number of gigabits per second in a virtual lane is sometimes referred to as a virtual lane width. Thus, in 100 Gb Ethernet, each virtual lane has a virtual lane width of 5 Gb. In other standards, such as 25 Gb Ethernet, the virtual lane width can be said to be 25 Gb, since 25 Gb Ethernet includes a single electrical lane with no virtual lane markers.
When an Ethernet standard with different numbers of virtual lanes and virtual lane widths from a current or previous Ethernet standard is proposed, switch manufacturers or their respective chip vendors produce chips to implement the new standards. Before the switches and their associated chips can be used in live networks, the switches and chips must be tested for performance and functional compliance with the standard. One way to perform such testing is to send simulated traffic to the switch and monitor how the switch responds to the simulated traffic. In order to send simulated traffic to a switch and monitor its performance and functional compliance, transceiver chips that transmit and receive the simulated traffic with the appropriate number of virtual lanes and lane widths must be produced. When test interface chips for a particular standard are not yet available, it may be desirable to produce a test system with chipsets configured for one standard and its associated number of virtual lanes and virtual lane widths to test a next generation or other standard with different numbers of virtual lanes and different virtual lane widths. More generally, it may be desirable to produce a traffic generation system usable for test or non-test purposes with chipsets configured for one standard and its number of virtual lanes and lane widths to generate and send traffic that can be coherently detected by chipsets of a different standard with different numbers of virtual lanes and lane widths.
One problem with utilizing a chipset designed for one number of virtual lanes and associated lane widths to generate and send traffic to a device designed to operate at another number of virtual lanes and associated virtual lane widths is that the receiver must know precisely where bits will be allocated by the transmitter in order to properly reassemble the transmitted data. For example, it may be desirable to generate or forward traffic to a 25 Gb Ethernet switch. Unlike 100 Gb Ethernet, which includes twenty 5 Gb virtual lanes, each identified by a virtual lane marker, 25 Gb Ethernet consists of a single 25 Gb electrical lane with no virtual lane markers.
In one example, it may be desirable to use the existing 100 Gb Ethernet architecture to generate and coherently receive 25 Gb Ethernet traffic. However, because electrical components and the optical network itself generate skew between virtual lanes and 25 Gb Ethernet does not include virtual lane markers for identifying virtual lanes and removing such skew, modifications to the existing architecture may be required to perform such testing. In general, any time it is desirable to convert between standards with different virtual lane widths, transmitter and receiver modifications may be required to account for different amounts of skew between virtual lanes.
Accordingly, there exists a need for a device that compensates for skew between electrical lanes to allow coherent detection by a receiver.